This invention relates generally to memories and more particularly to memories having error detection and correction.
As is known in the art, error correction and detection codes are used with data to correct errors which may occur in propagation of the data, or to at least detect the presence of an error in the propagated data. For example, a Reed-Solomon or Hamming code may be used to provide redundant bits to data. The data, with the redundant code, is fed through a portion of a system. When outputted from the system, the redundant code together with the data enables an error correction and detection (EDAC) process to reconstruct the data if one bit has been corrupted and to detect an error in the data if two bits have been corrupted. Such is sometimes known as SECDED, i.e., Single Error Correction/Double Error Detection.
In many data processing systems, random access memories (RAMs), such as dynamic RAMs (i.e., DRAMs) are used and the data with associated redundant bits is stored as a word in the DRAM. After the word is read from the DRAM it passes through an EDAC to correct or detect errors which may have occurred in the DRAM. In the past, these DRAMs were arranged in an N.times.1 bit arrangement, where N may is the number of bits in the word. One application for these DRAMS is as cache memories where data is passed from a disk drive to a computer through an interface having controllers. For example, one system includes a large mainframe computer which requires large capacity data storage. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system. One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or "front end", controllers and "back end" disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled "System and Method for Disk Mapping and Data Retrieval", inventors Moshe Yansi, Natan Vishlitzky, Bruno Altersu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. patent, the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In such system, the SECDED is provided on the controllers to encode data being sent to the cache memory and to check the integrity of data retrieved from the cache. Thus, as noted above, in the past, theses DRAMs were arranged in an N.times.1 bit arrangement, where N is the number of bits in the word stored in the DRAM, for example, N may be 72. More particularly, each data is, in this example, 64 bits and has associated with it 8 redundant bits to thereby constitute a word having 72 bits. Thus, the DRAM is made up of 72 DRAM packages, P.sub.1 -P.sub.72, each package having one bit word length and adapted to store k, one bit words, W.sub.0 -W.sub.x, where k may be 16 megabits, for example, as shown in FIG. 1A. Thus, packages P.sub.1 -P.sub.64 store each store a corresponding one of the 64 data bits and each one of the packages P.sub.65 -P.sub.72 store a corresponding one of the redundant bits for the EDAC. Today, however, the use of M.times.4 bit arrangements are being used for the DRAMs. Thus, each DRAM package is adapted to store, four bit words, W.sub.0 -W.sub.x, as shown in FIG. 1B. That is, each one of the packages P'.sub.1 -P'.sub.16 stores a correspond set of four bits (i.e., a nibble) of the 64 data bits, and packages P'.sub.17 and P'.sub.18 each store a set of four bits of the 8 redundant bits for EDAC. As noted in the system above, the EDAC is performed on the controllers. However, the EDAC used in the controllers is a SECDED EDAC and are not adapted to detect a failed M.times.4 type DRAM package. One technique suggested is to change the EDAC on the controllers so that they will be able to correct for nibble errors; however, such is relatively expensive, particularly if retro-fitting, or up-dating of existing equipment is not desired.